Ich erhalte den Fehler "[Synth 8-2519] teilweise zugeordnetes formales q8 kann kein tatsächliches OPEN haben" - dieser Fehler gilt für die Zeile Q8(0) => OPEN,und alle ähnlichen OPEN-Zuweisungen. Ich verwende diese, weil das IN_FIFO-Element zu groß für die Daten ist, die ich durch es senden möchte.
Die vollständige Entitätsinstanziierung ist unten für den Kontext (Entschuldigung für den langen Code unten, es ist nur eine große Menge von Zuweisungen).
IN_FIFO_LVDS_A_inst : IN_FIFO
generic map (
ALMOST_EMPTY_VALUE => 1, -- Almost empty offset (1-2)
ALMOST_FULL_VALUE => 1, -- Almost full offset (1-2)
ARRAY_MODE => "ARRAY_MODE_4_X_4", -- ARRAY_MODE_4_X_8, ARRAY_MODE_4_X_4
SYNCHRONOUS_MODE => "FALSE" -- Clocks synchronous to each other (FALSE)
)
port map (
-- FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
ALMOSTEMPTY => ALMOSTEMPTY_LVDS_S, -- 1-bit output: Almost empty
ALMOSTFULL => ALMOSTFULL_LVDS_S, -- 1-bit output: Almost full
EMPTY => EMPTY_LVDS_S, -- 1-bit output: Empty
FULL => FULL_LVDS_S, -- 1-bit output: Full
-- Q0-Q9: 8-bit (each) output: FIFO Outputs
Q0(0) => a_line_lvds_i_1_sync_s(13) , -- output: Channel 0
Q0(1) => a_line_lvds_i_1_sync_s(12) ,
Q0(2) => a_line_lvds_i_1_sync_s(11) ,
Q0(3) => a_line_lvds_i_1_sync_s(10) ,
Q1(0) => a_line_lvds_i_1_sync_s(9) , -- output: Channel 1
Q1(1) => a_line_lvds_i_1_sync_s(8) ,
Q1(2) => a_line_lvds_i_1_sync_s(7) ,
Q1(3) => a_line_lvds_i_1_sync_s(6) ,
Q2(0) => a_line_lvds_i_1_sync_s(5) , -- output: Channel 2
Q2(1) => a_line_lvds_i_1_sync_s(4) ,
Q2(2) => a_line_lvds_i_1_sync_s(3) ,
Q2(3) => a_line_lvds_i_1_sync_s(2) ,
Q3(0) => a_line_lvds_i_1_sync_s(1) , -- output: Channel 3
Q3(1) => a_line_lvds_i_1_sync_s(0) ,
Q3(2) => a_line_lvds_i_0_sync_s(17) ,
Q3(3) => a_line_lvds_i_0_sync_s(16) ,
Q4(0) => a_line_lvds_i_0_sync_s(15) , -- output: Channel 4
Q4(1) => a_line_lvds_i_0_sync_s(14) ,
Q4(2) => a_line_lvds_i_0_sync_s(13) ,
Q4(3) => a_line_lvds_i_0_sync_s(12) ,
Q5(0) => a_line_lvds_i_0_sync_s(11) , -- output: Channel 5
Q5(1) => a_line_lvds_i_0_sync_s(10) ,
Q5(2) => a_line_lvds_i_0_sync_s(9) ,
Q5(3) => a_line_lvds_i_0_sync_s(8) ,
Q6(0) => a_line_lvds_i_0_sync_s(7) , -- output: Channel 6
Q6(1) => a_line_lvds_i_0_sync_s(6) ,
Q6(2) => a_line_lvds_i_0_sync_s(5) ,
Q6(3) => a_line_lvds_i_0_sync_s(4) ,
Q7(0) => a_line_lvds_i_0_sync_s(3) , -- output: Channel 7
Q7(1) => a_line_lvds_i_0_sync_s(2) ,
Q7(2) => a_line_lvds_i_0_sync_s(1) ,
Q7(3) => a_line_lvds_i_0_sync_s(0) ,
Q8(0) => OPEN , -- output: Channel 8
Q8(1) => OPEN ,
Q8(2) => OPEN ,
Q8(3) => OPEN ,
Q9(0) => OPEN , -- output: Channel 9
Q9(1) => OPEN ,
Q9(2) => OPEN ,
Q9(3) => OPEN ,
-- D0-D9: 4-bit (each) input: FIFO inputs
D0(0) => a_line_lvds_i_1_s(13) , -- input: Channel 0
D0(1) => a_line_lvds_i_1_s(12) ,
D0(2) => a_line_lvds_i_1_s(11) ,
D0(3) => a_line_lvds_i_1_s(10) ,
D1(0) => a_line_lvds_i_1_s(9) , -- input: Channel 1
D1(1) => a_line_lvds_i_1_s(8) ,
D1(2) => a_line_lvds_i_1_s(7) ,
D1(3) => a_line_lvds_i_1_s(6) ,
D2(0) => a_line_lvds_i_1_s(5) , -- input: Channel 2
D2(1) => a_line_lvds_i_1_s(4) ,
D2(2) => a_line_lvds_i_1_s(3) ,
D2(3) => a_line_lvds_i_1_s(2) ,
D3(0) => a_line_lvds_i_1_s(1) , -- input: Channel 3
D3(1) => a_line_lvds_i_1_s(0) ,
D3(2) => a_line_lvds_i_0_s(17) ,
D3(3) => a_line_lvds_i_0_s(16) ,
D4(0) => a_line_lvds_i_0_s(15) , -- input: Channel 4
D4(1) => a_line_lvds_i_0_s(14) ,
D4(2) => a_line_lvds_i_0_s(13) ,
D4(3) => a_line_lvds_i_0_s(12) ,
D5(0) => a_line_lvds_i_0_s(11) , -- input: Channel 5
D5(1) => a_line_lvds_i_0_s(10) ,
D5(2) => a_line_lvds_i_0_s(9) ,
D5(3) => a_line_lvds_i_0_s(8) ,
D5(4) => '0' ,
D5(5) => '0' ,
D5(6) => '0' ,
D5(7) => '0' ,
D6(0) => a_line_lvds_i_0_s(7) , -- input: Channel 6
D6(1) => a_line_lvds_i_0_s(6) ,
D6(2) => a_line_lvds_i_0_s(5) ,
D6(3) => a_line_lvds_i_0_s(4) ,
D6(4) => '0' ,
D6(5) => '0' ,
D6(6) => '0' ,
D6(7) => '0' ,
D7(0) => a_line_lvds_i_0_s(3) , -- input: Channel 7
D7(1) => a_line_lvds_i_0_s(2) ,
D7(2) => a_line_lvds_i_0_s(1) ,
D7(3) => a_line_lvds_i_0_s(0) ,
D8(0) => '0' , -- input: Channel 8
D8(1) => '0' ,
D8(2) => '0' ,
D8(3) => '0' ,
D9(0) => '0' , -- input: Channel 9
D9(1) => '0' ,
D9(2) => '0' ,
D9(3) => '0' ,
-- FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
RDCLK => clk_150MHz_thruline_s , -- 1-bit input: Read clock
RDEN => '1' , -- 1-bit input: Read enable
RESET => bus_a_reset_pl(1) , -- 1-bit input: Reset
WRCLK => dclk_a_pll_clk0 , -- 1-bit input: Write clock
WREN => '1' -- 1-bit input: Write enable
);
Ich bin verwirrt darüber, warum sich der Synthesizer in Vivado darüber beschwert - sicherlich kann ich unbenutzte Ausgänge auf OPEN und unbenutzte Eingänge auf '0' setzen. Gibt es etwas Besonderes am IN_FIFO?
In VHDL können Sie kein einzelnes Element eines Ports mit verbinden open. Sie müssen entweder den gesamten Port mit verbinden openoder einige Elemente mit Ihren beabsichtigten Signalen und andere mit nicht verwendeten Signalen verbinden.
Sie haben also ein paar Möglichkeiten:
Q8 => open, -- Just associate the whole port with `open`
wenn Sie aus irgendeinem Grund eine individuelle Assoziation verwenden müssen:
signal unused_q8 : std_logic_vector(3 downto 0);
Q8(0) => unused_q8(0),
Q8(1) => unused_q8(1),
Q8(2) => unused_q8(2),
Q8(3) => unused_q8(3),
Das häufigere Szenario, in dem diese Fehlermeldung angezeigt wird, würde folgendermaßen aussehen:
Q8(2 downto 0) => q8_out(2 downto 0),
Q8(3) => open,
Hier haben wir einige Elemente eines Ausgangsvektors mit einem Signal verknüpft und andere mit open. Dies wird nicht unterstützt.
Toni M
BenAdamson
Q8 => OPEN,anstelle vonQ8(0) => OPEN, Q8(1) => OPEN,... etc die Warnmeldung beseitigt zu haben. Anscheinend hasst es die Vivado-Synthese, einzelne Zeilen zu öffnen, obwohl der Code logischerweise dasselbe tut?!Toni M