Warum erzeugt dieser Verilog-Code keine Ausgabe auf meinem FPGA?

Ich versuche, Verilog selbst zu lernen, indem ich DE1-Soc und die Altera University Program Labs verwende. Ich bin im allerersten Labor und versuche, einen 4 Bit breiten Multiplexer mit zwei Eingängen zu bauen. Ich habe diesen Verilog-Code geschrieben, um die Schalter 3-0 und 7-4 zu den beiden 4-Bit-Eingängen und den Schalter 9 zur Auswahl sowie die LEDs 3-0 zur Anzeige zu machen.

Ich wollte Kapselung verwenden, also machte ich die Eingänge des Top-Level-Moduls zu den Schaltern und die Ausgänge zu den LEDs und dann benutzte ich Drähte, um die Signale zu leiten.

Aus irgendeinem Grund synthetisiert es gut, aber die LEDs auf dem FPGA sind alle aus, egal was ich tue.

Hier ist der Verilog-Code:

module part2(SW, LEDR);

    //input and output declarations
    input [9:0] SW; // all 10 switches on DE1-SoC board
    output [9:0] LEDR; //all 10 LEDs on DE1-SoC board

    //input and output wires
    wire [3:0]X; //routes first four bit input
    wire [3:0]Y; //routes second four bit input
    wire s; // routes select
    wire [3:0]M; //routes output to LEDS

    //wire assignments
    assign X = SW[3:0];
    assign Y = SW[7:4];
    assign s = SW[9];
    assign M = LEDR[3:0];

    //mux declarations
    Mux2_1(s, X[0], Y[0], M[0]);
    Mux2_1(s, X[1], Y[1], M[1]);
    Mux2_1(s, X[2], Y[2], M[2]);
    Mux2_1(s, X[3], Y[3], M[3]);
endmodule

module Mux2_1(s, x, y, m); //2:1 mux

    //input and output declarations
    input s;
    input x;
    input y;

    output m;

    //assignment
    assign m = (~s & x) | (s & y);
endmodule

Ich habe die Zuordnungen überprüft und sie sollten vollständig korrekt sein, aber für den Fall, dass Sie dies überprüfen möchten, hier meine Zuordnungen für das DE1-SoC-Board:

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Altera and sold by Altera or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
# Date created = 11:52:22  March 25, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#       part2_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#       assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY part2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:52:22  MARCH 25, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE part2.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_V16 -to LEDR[0]
set_location_assignment PIN_W16 -to LEDR[1]
set_location_assignment PIN_V17 -to LEDR[2]
set_location_assignment PIN_V18 -to LEDR[3]
set_location_assignment PIN_W17 -to LEDR[4]
set_location_assignment PIN_W19 -to LEDR[5]
set_location_assignment PIN_Y19 -to LEDR[6]
set_location_assignment PIN_W20 -to LEDR[7]
set_location_assignment PIN_W21 -to LEDR[8]
set_location_assignment PIN_Y21 -to LEDR[9]
set_location_assignment PIN_AB12 -to SW[0]
set_location_assignment PIN_AC12 -to SW[1]
set_location_assignment PIN_AF9 -to SW[2]
set_location_assignment PIN_AF10 -to SW[3]
set_location_assignment PIN_AD11 -to SW[4]
set_location_assignment PIN_AD12 -to SW[5]
set_location_assignment PIN_AE11 -to SW[6]
set_location_assignment PIN_AC9 -to SW[7]
set_location_assignment PIN_AD10 -to SW[8]
set_location_assignment PIN_AE12 -to SW[9]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top