Wie aktualisiere ich ein Quartus II-Projekt von SOPC auf QSys?

Ich verstehe meine Fehler in QSys nicht, können Sie mir helfen? Ich versuche, diese Übung durchzugehen: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf

Wenn ich in Qsys die Komponenten anschließe, erhalte ich den folgenden Fehler, der sich über die Verbindungen beschwert, die in den Anweisungen nicht angegeben sind, wie sie zu verdrahten sind:

Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.nios2_qsys_0: Exception slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.sram.avalon_slave_0: Interface must have an associated clock
Error: System.sram.avalon_slave_0: Interface must have an associated reset
Error: System.leds.avalon_slave_0: Interface must have an associated reset
Error: System.nios2_qsys_0.data_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.nios2_qsys_0.instruction_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.sram.avalon_slave_0: sram.avalon_slave_0 must declare an associated reset
Error: System.leds.avalon_slave_0: leds.avalon_slave_0 must declare an associated reset
Warning: System.leds.reset: Interface has no signals
Warning: System.sram: sram.conduit_end must be exported, or connected to a matching conduit.
Warning: System.leds: leds.conduit_end must be exported, or connected to a matching conduit.
Warning: System.jtag_uart_0: Interrupt sender jtag_uart_0.irq is not connected to an interrupt receiver

Ich kann die Anzahl der Fehler reduzieren, aber ich kann sie nicht auf 0 herunterbekommen, und ich weiß nicht wirklich, was ich tue, da es keine Anleitung zum Verbinden der Verbindungen gibt. Kannst du mir helfen?

An VHDL ist wahrscheinlich nichts auszusetzen.

library ieee;
use ieee.std_logic_1164.all;
entity de2_sram_controller is
port (
signal chipselect : in std_logic;
signal write, read : in std_logic;
signal address : in std_logic_vector(17 downto 0);
signal readdata : out std_logic_vector(15 downto 0);
signal writedata : in std_logic_vector(15 downto 0);
signal byteenable : in std_logic_vector(1 downto 0);
signal SRAM_DQ : inout std_logic_vector(15 downto 0);
signal SRAM_ADDR : out std_logic_vector(17 downto 0);
signal SRAM_UB_N, SRAM_LB_N : out std_logic;
signal SRAM_WE_N, SRAM_CE_N : out std_logic;
signal SRAM_OE_N : out std_logic
);
end de2_sram_controller;

architecture dp of de2_sram_controller is
begin

    SRAM_DQ <= writedata when write = '1'
                    else (others => 'Z');
    readdata <= SRAM_DQ;
    SRAM_ADDR <= address;
    SRAM_UB_N <= not byteenable(1);
    SRAM_LB_N <= not byteenable(0);
    SRAM_WE_N <= not write;
    SRAM_CE_N <= not chipselect;
    SRAM_OE_N <= not read;

end dp;


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity de2_led_flasher is
port (
clk : in std_logic;
reset_n : in std_logic;
read : in std_logic;
write : in std_logic;
chipselect : in std_logic;
address : in std_logic_vector(4 downto 0);
readdata : out std_logic_vector(15 downto 0);
writedata : in std_logic_vector(15 downto 0);
leds : out std_logic_vector(15 downto 0)
);
end de2_led_flasher;
architecture rtl of de2_led_flasher is
type ram_type is array(15 downto 0) of
std_logic_vector(15 downto 0);
signal RAM : ram_type;
signal ram_address, display_address : unsigned(3 downto 0);
signal counter_delay : unsigned(15 downto 0);
signal counter : unsigned(31 downto 0);
begin
ram_address <= unsigned(address(3 downto 0));
process (clk)
begin
if rising_edge(clk) then
if reset_n = '0' then
readdata <= (others => '0');
display_address <= (others => '0');
counter <= (others => '0');
counter_delay <= (others => '1');
else
if chipselect = '1' then
if address(4) = '0' then
if read = '1' then
readdata <= RAM(to_integer(ram_address));
elsif write = '1' then
RAM(to_integer(ram_address)) <= writedata;
end if;
else
if write = '1' then
counter_delay <= unsigned(writedata);
counter <= unsigned(writedata) & x"0000";
end if;
end if;
else
leds <= RAM(to_integer(display_address));
if counter = x"00000000" then
counter <= counter_delay & x"0000";
display_address <= display_address + 1;
else
counter <= counter - 1;
end if;
end if;
end if;
end if;
end process;
end rtl;

Ich habe meine Dateien hier hochgeladen .

Aktualisieren

Ich habe versucht, alle Änderungen aus der Antwort hier vorzunehmen, und ich erhalte immer noch einige Fehlermeldungen:

Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.nios2_qsys_0: Exception slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.nios2_qsys_0: Debug slave nios2_qsys_0.jtag_debug_module not connected to instruction_master.
Error: System.sram.avalon_slave_0: Interface must have an associated clock
Error: System.sram.avalon_slave_0: Interface must have an associated reset
Error: System.leds.avalon_slave_0: Interface must have an associated reset
Error: System.nios2.data_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.nios2.instruction_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.clk_0.clk_reset/leds.reset: Missing connection end (try "Remove Dangling Connections")
Error: System.sram.avalon_slave_0: sram.avalon_slave_0 must declare an associated reset
Error: System.leds.avalon_slave_0: leds.avalon_slave_0 must declare an associated reset
Warning: System.nios2: nios2.jtag_debug_module must be connected to an Avalon-MM master
Warning: System.sram: sram.conduit_end must be exported, or connected to a matching conduit.
Warning: System.jtag_uart_0: Interrupt sender jtag_uart_0.irq is not connected to an interrupt receiver

Aktualisierung 2

Jetzt versuche ich, dem Sram die Clock/Reset-Pins zuzuweisen, aber dafür gibt es keine Optionen: