Kann mein VHDL in Qsys nicht synthetisieren

Ich versuche, ein Modul mit VHDL für meinen DE2 zu erstellen, bei dem das Einfache ("Hello World") fast unmöglich ist. Der Hintergrund ist, dass ich versuche, Hello World auszuführen:

https://stackoverflow.com/questions/17966235/nios-2-hello-world/18267202?noredirect=1#18267202

http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf

Und jetzt folge ich der Anleitung, die mit meiner Version von Quartus II v13 nicht funktioniert:

Was bedeutet die Fehlermeldung? Mache ich etwas anderes falsch, was Sie anhand der Screenshots erkennen können?

Info: *******************************************************************
Info: Running Quartus II 32-bit Generate HDL Interface
Info:     Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info:     Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info:     Your use of Altera Corporation's design tools, logic functions 
Info:     and other software and tools, and its AMPP partner logic 
Info:     functions, and any output files from any of the foregoing 
Info:     (including device programming or simulation files), and any 
Info:     associated documentation or information are expressly subject 
Info:     to the terms and conditions of the Altera Program License 
Info:     Subscription Agreement, Altera MegaCore Function License 
Info:     Agreement, or other applicable license agreement, including, 
Info:     without limitation, that your use is for the sole purpose of 
Info:     programming logic devices manufactured by Altera and sold by 
Info:     Altera or its authorized distributors.  Please refer to the 
Info:     applicable agreement for further details.
Info:     Processing started: Fri Aug 16 09:52:04 2013
Info: Command: quartus_map not_a_project --generate_hdl_interface=C:/Users/student/Desktop/KTH/colombia/de2_sram_controller.vhd --source=C:/Users/student/Desktop/KTH/colombia/de2_sram_controller.vhd --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/student/AppData/Local/Temp/alt5933_4160154550827554259.dir/0002_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
Error: VHDL syntax error at de2_sram_controller.vhd(20) near text € File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(20) near text "€";  expecting ";" File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(20) near text ™ File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(21) near text € File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 21
Error: VHDL syntax error at de2_sram_controller.vhd(21) near text ™ File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 21
Warning: Quartus II 32-bit Generate HDL Interface was unsuccessful. 5 errors, 0 warnings
Error:     Peak virtual memory: 364 megabytes
Error:     Processing ended: Fri Aug 16 09:52:06 2013
Error:     Elapsed time: 00:00:02
Error:     Total CPU time (on all processors): 00:00:01
Error: No modules found when analyzing null.

Aktualisieren

Mein VHDL-Kompilierungsfehler ist jetzt dieser

Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Aug 16 17:48:44 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab3 -c lab3
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10500): VHDL syntax error at lab3.vhd(20) near text 
Error (10500): VHDL syntax error at lab3.vhd(20) near text "";  expecting ";"
Error (10500): VHDL syntax error at lab3.vhd(20) near text 
Error (10500): VHDL syntax error at lab3.vhd(21) near text 
Error (10500): VHDL syntax error at lab3.vhd(21) near text 
Info (12021): Found 0 design units, including 0 entities, in source file lab3.vhd
Error (10430): VHDL Primary Unit Declaration error at de2_sram_controller.vhd(3): primary unit "de2_sram_controller" already exists in library "work"
Error (10784): HDL error at lab3.vhd(3): see declaration for object "de2_sram_controller"
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text 
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text "";  expecting ";"
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text 
Error (10500): VHDL syntax error at de2_sram_controller.vhd(23) near text 
Error (10500): VHDL syntax error at de2_sram_controller.vhd(23) near text 
Info (12021): Found 0 design units, including 0 entities, in source file de2_sram_controller.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 12 errors, 1 warning
    Error: Peak virtual memory: 476 megabytes
    Error: Processing ended: Fri Aug 16 17:48:45 2013
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 14 errors, 1 warning

Der Code ist

library ieee;
use ieee.std_logic_1164.all;
entity de2_sram_controller is
port (
signal chipselect : in std_logic;
signal write, read : in std_logic;
signal address : in std_logic_vector(17 downto 0);
signal readdata : out std_logic_vector(15 downto 0);
signal writedata : in std_logic_vector(15 downto 0);
signal byteenable : in std_logic_vector(1 downto 0);
signal SRAM_DQ : inout std_logic_vector(15 downto 0);
signal SRAM_ADDR : out std_logic_vector(17 downto 0);
signal SRAM_UB_N, SRAM_LB_N : out std_logic;
signal SRAM_WE_N, SRAM_CE_N : out std_logic;
signal SRAM_OE_N : out std_logic
);
end de2_sram_controller;

architecture dp of de2_sram_controller is
begin

    SRAM_DQ <= writedata when write = ’1’
                    else (others => ’Z’);
    readdata <= SRAM_DQ;
    SRAM_ADDR <= address;
    SRAM_UB_N <= not byteenable(1);
    SRAM_LB_N <= not byteenable(0);
    SRAM_WE_N <= not write;
    SRAM_CE_N <= not chipselect;
    SRAM_OE_N <= not read;

end dp;